1. Field of the Invention
This invention relates to a fuse cutting test circuit, fuse cutting test method, and semiconductor circuit, and in particular relates to a test circuit and test method to confirm in detail the state of fuse cutting in a semiconductor storage device comprising redundant memory cells.
2. Description of the Related Art
In semiconductor storage device manufacturing processes, techniques to replace memory cells in which faults have occurred with redundant memory cells have become essential. As the method of replacement, generally a fuse is broken to perform replacement. There exist both laser beam melting-type fuses, in which the fuse is irradiated by a laser beam from outside to break the wiring, and voltage application-type fuses, in which a high voltage is applied to break the wiring or to destroy an insulating film. As process miniaturization advances and semiconductor storage devices increase in capacity, such techniques are becoming increasingly important, and fuses are being used not only in semiconductor storage devices but also to perform various switching or adjustment of circuit states.
In the above-described techniques, when cutting a fuse which is to be broken, there may be cases in which another fuse which is not to be broken is erroneously broken, as well as cases in which a fuse which is to be broken is not broken completely. For this reason, techniques for performing tests to determine whether a fuse which is to be broken has properly been broken through cutting treatment, and whether fuses which are not to be broken exist properly, are increasing in importance together with the above techniques. Conventional fuse circuits and test methods for such circuits are for example disclosed in Japanese Unexamined Patent Application Publication No. 5-242691.
As described in the above document, among inspections of fuse cutting faults, there is for example a fault mode in high-speed SRAM products which cannot be detected if the power supply is not raised gradually (slow-rise faults). This fault mode occurs when a fuse which should have been broken is not broken completely. Specifically, when a fuse is not broken completely, the fuse functions as a high-resistance. In the circuit which generates logic according to whether the fuse is broken or not broken, the signal in the stage following the fuse becomes unstable.
The circumstances of the above slow-rise fault are explained in further detail using FIG. 7 and FIG. 8. FIG. 7 and FIG. 8 are circuit diagrams showing the configuration of conventional fuse circuits. In the circuit shown in FIG. 7, the fuse 1 and a resistance 2 are connected in series between the power supply VCC and ground, and the potential at the point of connection of the fuse 1 and resistance 2 is inverted using an inverter 3 and output. The NMOS device 4 is a transistor to prevent floating; the capacitances 5 and 6 are used to prevent output of an erroneous signal due to transient operation of the output of the inverter 3 when the power supply rise is rapid, and these capacitances are Cv and Cg respectively.
FIG. 8 is a circuit diagram showing a state in which the fuse 1 in FIG. 7 is broken. After the fuse 1 has not been completely broken, and is only imperfectly broken, the remaining resistance after cutting of the fuse 1 is Rfcut, and the remaining compensating resistance of the resistance 2 is Rg. Cvi and Cgo are parasitic capacitances.
In a circuit such as that of FIG. 7, when the fuse 1 is not completely broken, the fuse 1 is regarded as a high resistance, and it is unclear whether the potential appearing between the fuse 1 and resistance 2 will be selected as an “H” or as an “L” potential. For example, as shown in FIG. 9, when the power supply is raised rapidly, the program-circuit contact point (OUT) immediately after power supply input takes on a capacitance-divided potential and the NMOS device 4 is turned on, so that the signal becomes stable.
To explain in further detail, when the fuse 1 is not completely broken, the fuse 1 enters a high-resistance state as explained above, and the potential between the fuse 1 and resistance 2 rises via the fuse 1. However, if the power supply is raised rapidly, prior to exceeding the threshold at which the potential between the fuse 1 and resistance 2 is recognized as “H”, the inverter 3 operates in a state in which the potential is at “L”, so that the output of the inverter 3 is “H” and the NMOS device 4 is turned on. Then the potential IN shown in FIG. 8 is grounded, so that the output from the inverter 3 stabilizes at “H”, and a signal is output indicating that the fuse 1 is broken.
On the other hand, when more time is taken to raise the power supply level, operation is stabilized substantially when the resistance-divided potential IN at the program-circuit connection point exceeds the threshold, as shown in FIG. 10. In this case, the value “L” indicating that the fuse is not broken, is obtained as the output. This potential is opposite to the expected value “H” indicating that the fuse has been broken.
To explain in further detail, when the fuse 1 is not completely broken and is in a high-resistance state, the rise in the potential between the fuse 1 and resistance 2 via the fuse 1 is similar to the case of a rapid rise in the power supply level. However, when time is taken to raise the power supply level, time elapses until the inverter 3 begins operation, and before the inverter 3 operates the potential IN shown in FIG. 8 may in some cases exceed the threshold recognized as “H”. In such cases, the output of the inverter 3 stabilizes at “L”, and a signal is output indicating that the fuse 1 is not broken.
In this way, in order to detect incomplete cutting of the fuse 1, a test pattern in which time is taken while raising the power supply level (a slow-rise test pattern) is necessary. When a slow-rise test pattern is used, the power supply must be raised in millisecond-order time, and the time required for tests is lengthened. When using a slow-rise test pattern, if the inverter 3 operates before the potential IN exceeds the threshold recognized as “H”, then the potential IN is grounded, and so a signal is output indicating that the fuse 1 is broken; hence stable test results are not obtained.